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target datasheet 1 4.00 hys 72dxxx0gr registered ddr-i sdram-modules 2.5 v 184-pin registered ddr-i sdram modules 256mb, 512mb & 1 gbyte modules preliminary datasheet rev. 0.9 the hys 72dxx000gr are industry standard 184-pin 8-byte dual in-line memory modules (dimms) organized as 32m 72, 64m 72 and 128m 72. the memory array is designed with double data rate synchronous drams (2.5v ddr-i) for ecc applications. all control and address signals are re-driven on the dimm using register devices and a pll for the clock distribution. this reduces capacitive loading to the system bus, but adds one cycle to the sdram timing. a variety of decoupling capacitors are mounted on the pc board. the dimms feature serial presence detect based on a serial e 2 prom device using the 2-pin i 2 c protocol. the first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. ? 184-pin registered 8-byte dual-in-line ddr-i sdram module for pc and server main memory applications ? one bank 32m 72, 64m x 72 and two bank 64m x 72, 128m 72 organization ? jedec standard double data rate synchronous drams (ddr-i sdram) single + 2.5 v ( 0.2 v) power supply ? built with 256mbit ddr-i sdrams in 66- lead tsopii package ? programmable cas latency, burst length, and wrap sequence (sequential & interleave) ? auto refresh (cbr) and self refresh ? all inputs and outputs sstl_2 compatible ? re-drive for all input signals using register and pll devices. ? serial presence detect with e 2 prom ? jedec standard mo-161 form factor: 133.35 mm 43.18 mm 4.00 mm (8.00 mm when stacked) ? jedec standard reference layout: rev 0.9 of r/c a, r/c b and rc c ? gold plated contacts ? performance: -7 -7.5 -8 unit component speed grade pc266a pc266b pc200 module speed grade pc2100 pc2100 pc1600 f ck clock frequency (max.) @ cl = 2.5 143 133 125 mhz f ck clock frequency (max.) @ cl = 2 133 100 100 mhz
hys 72dxx0x0gr registered ddr-i sdram-modules target datasheet 2 4.00 note: all part numbers end with a place code (not shown), designating the silicon-die revision. reference information available on request. example: hys 72d32000gr-8-a, indicating rev.a die are used for sdram components. ordering information type compliance code description sdram technology pc266a : hys 72d32000gr-7 pc266ar-20330-a1 one bank 256 mb reg. dimm 256 mbit hys 72d64000gr-7 pc266ar-20330-b1 one bank 512 mb reg. dimm 256 mbit hys 72d64020gr-7 pc266ar-20330-a1 two banks 512 mb reg. dimm 256 mbit hys 72d128020gr-7 pc266ar-20330-c1 two banks 1 gbyte reg. dimm 256 mbit (stacked) pc266b: hys 72d32000gr-7.5 pc266br-25330-a1 one bank 256 mb reg. dimm 256 mbit hys 72d64000gr-7.5 pc266br-25330-b1 one bank 512 mb reg. dimm 256 mbit hys 72d64020gr-7.5 pc266br-25330-a1 two banks 512 mb reg. dimm 256 mbit hys 72d128020gr-7.5 pc266br-25330-c1 two banks 1 gbyte reg. dimm 256 mbit (stacked) pc200r: hys 72d32000gr-8 pc200r-20220-a1 one bank 256 mb reg. dimm 256 mbit hys 72d64000gr-8 pc200r-20220-b1 one bank 512 mb reg. dimm 256 mbit hys 72d64020gr-8 pc200r-20220-a1 two banks 512 mb reg. dimm 256 mbit hys 72d128020gr-8 pc200r-20220-c1 two banks 1 gbyte reg. dimm 256 mbit (stacked)
hys 72dxx0x0gr registered ddr-i sdram-modules target datasheet 3 4.00 pin definitions and functions a0 - a12 address inputs v dd power (+ 2.5 v) ba0, ba1 bank selects v ss ground dq0 - dq63 data input/output v ddq i/o driver power supply cb0 - cb7 check bits (x72 organization only) v ddid vdd indentification flag ras row address strobe v ddspd eeprom power supply cas column address strobe v ref i/o reference supply we read/write input scl serial bus clock cke0 - cke1 clock enable sda serial bus data line dqs0 - dqs8 sdram low data strobes sa0 - sa2 slave address select clk, clk differential clock input wp write prodect flag dm0 - dm8 dqs9 - dqs17 sdram low data mask/ high data strobes nc no connect s0 - s3 chip selects reset reset pin (forces register inputs low) address format density organization memory banks sdrams # of sdrams # of row/bank/ columns bits refresh period interval 256 mb 32m x 72 1 32m x 8 9 13/2/10 8k 64 ms 7.8 m s 512 mb 64m 72 1 64m 4 18 13/2/11 8k 64 ms 7.8 m s 512 mb 64m x 72 2 32m x 8 18 13/2/10 8k 64 ms 7.8 m s 1 gb 128m 72 2 64m 4 36 13/2/11 8k 64 ms 7.8 m s
hys 72dxx0x0gr registered ddr-i sdram-modules target datasheet 4 4.00 pin configuration pin# symbol pin# symbol pin# symbol symbol 1 vref 48 a0 93 vss 140 dm8/dqs17 2 dq0 49 cb2 94 dq4 141 a10 3 vss 50 vss 95 dq5 142 cb6 4 dq1 51 cb3 96 vddq 143 vddq 5 dqs0 52 ba1 97 dm0/dqs9 144 cb7 6 dq2 53 dq32 98 dq6 145 vss 7 vdd 54 vddq 99 dq7 146 dq36 8 dq3 55 dq33 100 vss 147 dq37 9 nc 56 dqs4 101 nc 148 vdd 10 reset 57 dq34 102 nc 149 dm4/dqs13 11 vss 58 vss 103 a13 150 dq38 12 dq8 59 ba0 104 vddq 151 dq39 13 dq9 60 dq35 105 dq12 152 vss 14 dqs1 61 dq40 106 dq13 153 dq44 15 vddq 62 vddq 107 dm1/dqs10 154 ras 16 du (clk1) 63 we 108 vdd 155 dq45 17 du (clk1 ) 64 dq41 109 dq14 156 vddq 18 vss 65 cas 110 dq15 157 s0 19 dq10 66 vss 111 cke1 158 s1 20 dq11 67 dqs5 112 vddq 159 dm5/dqs14 21 cke0 68 dq42 113 ba2 160 vss 22 vddq 69 dq43 114 dq20 161 dq46 23 dq16 70 vdd 115 a12 162 dq47 24 dq17 71 nc, s2 116 vss 163 nc, s3 25 dqs2 72 dq48 117 dq21 164 vddq 26 vss 73 dq49 118 a11 165 dq52 27 a9 74 vss 119 dm2/dqs11 166 dq53 28 dq18 75 du (clk2) 120 vdd 167 nc 29 a7 76 du (clk2 ) 121 dq22 168 vdd 30 vddq 77 vddq 122 a8 169 dm6/dqs15 31 dq19 78 dqs6 123 dq23 170 dq54 32 a5 79 dqs0 124 vss 171 dq55 33 dq24 80 dq51 125 a6 172 vddq
hys 72dxx0x0gr registered ddr-i sdram-modules target datasheet 5 4.00 34 vss 81 vss 126 dq28 173 nc 35 dq25 82 vddid 127 dq29 174 dq60 36 dqs3 83 dq56 128 vddq 175 dq61 37 a4 84 dq57 129 dm3/dqs12 176 vss 38 vdd 85 vdd 130 a3 177 dm7/dqs16 39 dq26 86 dqs7 131 dq30 178 dq62 40 dq27 87 dq58 132 vss 179 dq63 41 a2 88 dq59 133 dq31 180 vddq 42 vss 89 vss 134 cb4 181 sa0 43 a1 90 nc 135 cb5 182 sa1 44 nc 91 sda 136 vddq 183 sa2 45 nc 92 scl 137 ck0 184 vddspd 46 vdd 138 ck0 47 nc 139 vss pin configuration pin# symbol pin# symbol pin# symbol symbol
hys 72dxx0x0gr registered ddr-i sdram-modules target datasheet 6 4.00 block diagram: one bank 32m 72 ddr-i sdram dimm module hys72d32000gr using x8 organized sdrams on raw card version a
hys 72dxx0x0gr registered ddr-i sdram-modules target datasheet 7 4.00 block diagram: two bank 64m 72 ddr-i sdram dimm modules hys 72d64020gr using x8 organized sdrams on raw card version a
hys 72dxx0x0gr registered ddr-i sdram-modules target datasheet 8 4.00 block diagram: one bank 64m 72 ddr-i sdram dimm modules hys 72d64000gr using x8 organized sdrams on raw card version b
hys 72dxx0x0gr registered ddr-i sdram-modules target datasheet 9 4.00 block diagram: two bank 128m 72 ddr-i sdram dimm modules hys 72d128020gr using x8 organized sdrams on raw card version c
hys 72dxx0x0gr registered ddr-i sdram-modules target datasheet 10 4.00 supply voltage levels parameter symbol limit values unit notes min. nom. max. device supply voltage v dd 2.3 2.5 2.7 v C output supply voltage v ddq 2.3 2.5 2.7 v 1) 1) under all conditions, v ddq must be less than or equal to v dd . input reference voltage v ref 1.15 1.25 1.35 v 2) 2) peak to peak ac noise on v ref may not exceed 2% v ref (dc) . v ref is also expected to track noise variations in v ddq . termination voltage v tt v ref C0.04 v ref v ref +0.04 v 3) 3) v tt of the transmitting device must track v ref of the receiving device. dc operating conditions (sstl_2 inputs) ( v ddq =2.5v, t a =70 c, voltage referenced to v ss ) parameter symbol limit values unit notes min. max. dc input logic high v ih (dc) v ref +0.18 v ddq +0.3 v 1) 1) the relationship between the v ddq of the driving device and the v ref of the receiving device is what determines noise margins. however, in the case of v ih (max) (input overdrive), it is the v ddq of the receiving device that is referenced. in the case where a device is implemented such that it supports sstl_2 inputs but has no sstl_2 outputs (such as a translator), and therefore no v ddq supply voltage connection, inputs must tolerate input overdrive to 3.0 v (high corner v ddq + 300 mv). dc input logic low v il (dc) C 0.30 v ref C0.18 v C input leakage current i il C 5 5 m a 2) 2) for any pin under test input of 0 v v in v ddq +0.3v. output leakage current i ol C 5 5 m a 2) capacitance (target, not verified) t a = 0 to 70 c; v dd =2.5v 0.2 v, f =1mhz parameter symbol limit values (max.) unit one bank modules two bank modules input capacitance (all inputs except clk,clk & cke) c in 10 20 pf input capacitance (clk, clk ) c clk 30 30 pf input capacitance (cke) c cke 17 30 pf input/output capacitance (dq0 - dq63, cb0 - cb7) c io 10 17 pf input capacitance (scl, sa0 - 2) c sc 88pf input/output capacitance (sda) c sd 88pf
hys 72dxx0x0gr registered ddr-i sdram-modules target datasheet 11 4.00 operating, standby and refresh currents (for reference only) (values apply to one sdram component and do not include register and pll) ( t a =0 to +70 c, v dd =2.5v0.2v) parameter symbol test condition speed unit notes C 7 C 7.5 C 8 operating current t rc = t rc(min) , t ck = min. active-precharge command without burst operation i cc1 1 bank operation cas latency = 2 100 90 70 ma 1), 2), 3) 1) these parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t ck and t rc . 2) the specified values are obtained with the output open. 3) input signals are changed once during three clock cycles. precharge standby current in power down mode i cc2p cke v il(max) , t ck = min., cs = v ih(min) 20 20 20 ma 1) precharge standby current in non-power down mode i cc2n cke 3 v ih(min) , t ck = min., cs = v ih (min) 50 45 40 ma 1), 3) no operating current (active state: 4 bank) i cc3p cke v il(max) , t ck = min. 30 30 30 ma 1) i cc3n cke 3 v ih(min) , t ck = min., cs = v ih (min) 65 60 55 ma 1), 3) operating current (burst mode) i cc4 t ck = min., read/write command cycling, multiple banks active, gapless data, bl = 4 140 120 100 ma 1), 2), 3) auto (cbr) refresh current i cc5 t ck = min., t rc = t rfc(min) cbr command cycling 155 135 110 ma 1), 4), 5) 4) 8192 refresh cycles in 64 ms. 5) minimum cycle time during auto refresh operation ( t ref ) is greater than minimum cycle time for read/write operation. self refresh current i cc6 cke 0.2 v 1 1 1 ma 1), 4)
hys 72dxx0x0gr registered ddr-i sdram-modules target datasheet 12 4.00 ac characteristics (for reference only) (values apply to the sdram component and do not include register, pll, or card wiring) ( t a =0 to+70 c, v dd =2.5v0.2v) parameter symbol -7 pc266a -7.5 pc266b -8 pc200 unit notes min. max. min. max. min. max. dq output access time from ck/ ck t ac C0.75 +0.75 C0.75 +0.75 C0.8 +0.8 ns C dqs output access time from ck/ ck t dqsck C0.75 +0.75 C0.75 +0.75 C0.8 +0.8 ns C clk high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 *tck C clk low level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 *tck C clock period cl = 2 t ck 7.52010201020ns 1) cl = 2.5 7 20 7.5 20 8 20 ns C cl=3 7207.520820nsC dq and dm input hold time t dh 0.5C 0.5C 0.6C nsC dq and dm input setup time t ds 0.5C 0.5C 0.6C nsC dq and dm input pulse width (for each input) t dipw 1.75C1.75C2CnsC data-out high-impedance from ck/ ck t hz C0.75 +0.75 C0.75 +0.75 C0.8 +0.8 ns C data-out low-impedance from ck/ ck t lz C0.75 +0.75 C0.75 +0.75 C0.8 +0.8 ns C dqs-dq skew t dqsq C+0.5C+0.5C+0.6nsC qh data-out hold time from dqs t qh thp-0.75 C thp-0.75 C thp-1.0 C ns 2) write command to first dqs latching transition t dqss 0.75 1.25 0.75 1.25 0.75 1.25 * t ck C dqs input valid time t dsl,h 0.40.60.40.60.40.6* t ck C mode register/extended mode register set cycle time t mrd 15C15C16CnsC write preamble setup time t wpres 0C0C0CnsC dqs hold time from ck/ck t wpreh 0.25 C 0.25 C 0.25 C * t ck C write postamble t wpst 0.40.60.40.60.40.6* t ck C input setup time (lvttl inputs) t is 0.9C 0.9C 1.2C ns 3) input hold time (lvttl inputs) t ih 0.9C 0.9C 1.2C ns 3) read preamble t rpre 0.91.10.91.10.91.1* t ck C read postamble t rpst 0.40.60.40.60.40.6* t ck C row active time t ras 45 120k 45 120k 50 120k ns C row cycle time r/w operation t rc 65C65C70CnsC auto refresh t rfc 75C75C80Cns 1) ras to cas delay t rcd 20C20C20CnsC row precharge time t rp 20C20C20CnsC row activate to row activate delay t rrd 15C15C15CnsC write recovery time t wr 15C15C15CnsC
hys 72dxx0x0gr registered ddr-i sdram-modules target datasheet 13 4.00 auto precharge write recovery + precharge time t dal 35 C35C35CnsC internal write to read command delay t wtr 1C1C1C* t ck C power down entry time t pdent t is + 1 clk 2 clk + t is CC t is + 1 clk 2 clk + t is ns C power down exit time t pdex t is + 1 clk 2 clk + t is CC t is + 1 clk 2 clk + t is ns C self refresh exit time t srex 200C 200C 200C cyclesC average periodic refresh intercal t ref C7.8C7.8C7.8 m sC clk transition time t t 0.5CCC0.5CnsC 1) minimum auto refresh cycle time is greater than minimum cycle time during normal read or write operation. 2) t hp is the lesser of t cl and t ch 3) these parameters guarantee device timing, but they are not necessarily tested on each device they may be guaranteed by design or tester correlation t is / t ih =0.9ns for pc266 are measured with command / address input slew rate of > 1.0v/ns for command / address input slew rate of > 0.5v/ns and < 1.0v/ns t is / t ih = 1.0ns should be guaranteed by design for pc200 t is / t ih = 1.2ns command / address input slew rate of 1.0v/ns is assumed slew rate is measured between v oh (ac) and v ol (ac) ck / ck slew rates are assumed to be > 1.0v/ns pulse width for command / address signals to be properly sampled at rising edges of clock shall be a minimum of 2.2ns environmental parameters symbol parameter rating units notes t opr operating temperature (ambient) 0 to +55 o c h opr operating humidity (relative) 10 to 90 % t stg storage temperature -50 to +100 o c 1) h stg storage humidity (without condensation) 5 to 95 % 1) barometric pressure (operating and storage) 105 to 69 k pascal 2) 1) stresses greater than those listed may cause permanent damage to the device. device functional operation at or above these con ditions is not implied. 2) up to 3000 m (9850 ft) ac characteristics (contd) (for reference only) (values apply to the sdram component and do not include register, pll, or card wiring) ( t a =0 to+70 c, v dd =2.5v0.2v) parameter symbol -7 pc266a -7.5 pc266b -8 pc200 unit notes min. max. min. max. min. max.
hys 72dxx0x0gr registered ddr-i sdram-modules target datasheet 14 4.00 package outlines module package jedec mo-161 ddr-i registered dimm modules raw card a 256mbyte modules (one physical bank)
hys 72dxx0x0gr registered ddr-i sdram-modules target datasheet 15 4.00 package outlines module package ddr-i registered dimm modules raw card a 512mbyte module with two physical banks
hys 72dxx0x0gr registered ddr-i sdram-modules target datasheet 16 4.00 package outlines module package ddr-i registered dimm modules raw card b 512mbyte module with one physical bank
hys 72dxx0x0gr registered ddr-i sdram-modules target datasheet 17 4.00 package outlines module package ddr-i registered dimm modules raw card c 1 gbyte module with two physical banks
hys 72dxx0x0gr registered ddr-i sdram-modules target datasheet 18 4.00 change list 11.99 rev.0.2 first target revision 0.2 1.00 rev.0.3 rev. 0.3 4.00 rev.0.9 rev. 0.9

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